1. Field of the Disclosure
The present disclosure relates to a memory system that may be incorporated into or used by a binary predictor, such as, but not limited to, a branch predictor.
2. Description of the Background of the Disclosure
Binary predictors are electronic circuits that analyze the outcomes of prior decisions in order to predict a future outcome of the same decision. The circuits have a number of potential applications including speculative run-ahead processing with inhibition, speculative resource access with inhibition in a synchronization environment, context switch control logic for a multithreaded system, and history based neural networks and neuromorphic circuits. In many cases, the circuits are used for branch prediction within modern microprocessors.
Many microprocessors are capable of executing instructions either sequentially or non-sequentially by skipping certain sequential instructions. These non-sequential instructions can be referred to as a branch. Sometimes a processor will jump to a particular branch based upon the result of an evaluation of a conditional jump statement. Until that conditional jump statement is evaluated, the processor cannot know to which branch a particular program will jump.
Without branch prediction, therefore, the processor must first execute the conditional jump statement before the processor can begin retrieving and executing the instructions associated with the target branch. Because it takes time to fetch the instructions associated with the target branch, this can result in a substantial delay in the execution of new instructions after a conditional jump statement is evaluated.
To minimize this delay, processors often incorporate branch predictors. A branch predictor attempts to predict the next instruction address to be executed by the microprocessor following a conditional jump statement. The predicted next instruction address is then fetched from the target branch to avoid delay in executing the branch's instructions. Sometimes the prediction is incorrect, in which case the delay described above may occur before the correct instruction can be fetched and executed.
Branch predictors often use DRAM to analyze the results of previous decisions. These memory devices are volatile, requiring regular refreshing to avoid information loss. The refreshing results in a substantial increase in energy consumed by the devices. Additionally, when reading values from the memory devices of conventional branch predictors, a significant amount of energy is consumed from the capacitive element storing the binary value. The amount of energy consumed by reading the stored value must then be recharged, again consuming energy.
In some cases, microprocessors use multiple threads of distinct execution paths to improve their efficiency. When one thread reaches a long latency operation that blocks the processor's execution flow, like a miss on a cache access in the memory hierarchy system, the processor will perform a context switch and start to execute a different thread on the central processing unit. Sometimes it can be advantageous for the processor to speculatively continue past a long latency operation on a thread's execution path to seek out additional long latency operations that can be performed in parallel.
A binary predictor could be used in such a system to make predictions of whether a processor should speculatively continue operating past a long latency operation, and perhaps whether the processor should switch to a new thread or simply conserve power.